High fT 30nm In0.7GaAs HEMT’s Beyond Lithography Limitations

Kim, Dae-Hyun and Noh, Hun-Hee and Yeon, Seong-Jin and Lee, Jae-Hak and Seo, Kwang-Seok (2004) High fT 30nm In0.7GaAs HEMT’s Beyond Lithography Limitations. In: Gallium Arsenide applications symposium. GAAS 2004, 11—12 Ottobre, Amsterdam.
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Abstract

Two types of 30nm In0.7GaAs HEMT has been successfully fabricated, using SiO2/SiNx sidewall process and BCB planarization, and ZEP flowing and sloped etching technique. The sidewall gate process was used to obtain more fine line in one type of device, which enabled to lessen the initial line length to half by this process, and to fill the schottky gate effectively in a narrow gate line, the sputtered tungsten (W) metal was utilized instead of evaporation method. To reduce the parasitic capacitance through dielectric layers and gate metal resistance, the etch-backed BCB was used for the assisting layer of gate top head. The other 30nm device could be fabricated with inverted double-exposure & double-develop method when initial defined 100nm could be reduced to 30nm by using ZEP flowing and sloped etching. The fabricated two 30nm In0.7GaAs HEMT’s showed similar characteristics such as fT above 400GHz. We believe that the developed technology will be directly applicable to an InGaAs nano-HEMT with finer gate length if the initial line length will be reduced below 60nm range.

Abstract
Document type
Conference or Workshop Item (Paper)
Creators
CreatorsAffiliationORCID
Kim, Dae-Hyun
Noh, Hun-Hee
Yeon, Seong-Jin
Lee, Jae-Hak
Seo, Kwang-Seok
Subjects
DOI
Deposit date
16 Jun 2005
Last modified
17 Feb 2016 14:13
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