Design and performance assessment of a multigigabit clock-recovery circuit

Lima, Mario J. ; Monteiro, Paulo P. ; Matos, J. Nuno ; da Rocha, Jose F. ; Teixeira, Antonio (1998) Design and performance assessment of a multigigabit clock-recovery circuit. In: Gallium Arsenide Applications Symposium. GAAS 1998, 5-6 October 1998, Amsterdam, The Netherlands.
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Abstract

This paper presents the design and experimental results of a nonlinear circuit and a tuned amplifier developed in the same GaAs monolithic microwave integrated circuit (MMIC), used in a 20 Gsymbol/s open-loop clock recovery unit. The nonlinearity is an unbalanced structure and its input stage performs the necessary signal formatting to reduce the recovered clock jitter, avoiding the use of additional pre-filtering. Both circuits were integrated in the same MMIC in order to improve the reliability, performance and to reduce the size and cost. Performance assessment of the clock recovery unit consisting of the two designed circuits and a high-Q bandpass filter is carried out, considering two different line codings, binary NRZ (20 Gbit/s) and 4-level (40 Gbit/s).

Abstract
Tipologia del documento
Documento relativo ad un convegno o altro evento (Atto)
Autori
AutoreAffiliazioneORCID
Lima, Mario J.
Monteiro, Paulo P.
Matos, J. Nuno
da Rocha, Jose F.
Teixeira, Antonio
Settori scientifico-disciplinari
DOI
Data di deposito
16 Feb 2006
Ultima modifica
17 Feb 2016 14:35
URI

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