10 GHz ultra-high speed GaAs decision circuit design

Lee, M. ; Kim, Y. M. (1996) 10 GHz ultra-high speed GaAs decision circuit design. In: Gallium Arsenide Applications Symposium. GAAS 1996, 5-6 June 1996, Paris, France.
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Giga-bit level IC design has already been progressed by GaAs MESFET technology. This work is to present a lOGbps ultra-high speed design with sensitive decision circuit using 0.5 um gate MESFET technology. The decision circuit is basically consisted of Master-Slave type D-FF, source-coupled FET differential amplifier named Source-Coupled FET Logic (SCFL) circuit. This GaAs digital SCFL circuit includes two FETs(E-mode MESFET and D-mode MESFET) and also includes some of resistors and diodes between input signals and ground. Source-follower generally minimizes the load of the SCFL and is included in the output node to improve the performance. Based on the fabricated 0.5 um devices, process parameters are successfully extracted and optimized to check for 10 GHz operation from the D-FF SCFL decision circuit using circuit simulator before real GaAs IC process fabrication. The GaAs SCFL circuit was operated at 10 Gbps ultra-high speed level, which is designed for future high speed optical receivers.

Document type
Conference or Workshop Item (Paper)
Lee, M.
Kim, Y. M.
Deposit date
16 Feb 2006
Last modified
17 Feb 2016 14:37

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