Abstract

For the implementation of high-complexity circuits operating at high speed, low-power circuits are essential in order to meet chip level and systems level power dissipation requirements. This paper presents the designs of a multiplexer and a demultiplexer. The circuits are implemented by using two-phase dynamic FET logic (TDFL). Two chips were designed. Each chip comprises a small system integrating normal TDFL logic, pass gates and domino logic as well as clock drivers. Measurements show that the multiplexer operates at 300MHz and the demultiplexer operates at 550MHz