Abstract

The architecture and design of a GaAs multi-GHz two-stage programmable decimator are presented. A transistor-level realisation of the first stage( the comb decimator) and the cell count of the second stage decimator in a 0.3 um GaAs/AlGaAs HEMT E/D process are considered. The performance has been calculated through measurements made on two 12-bit adders using SDCFL and DCFL gates. An alternating carry state technique allows a speed of 2GHz to be obtained with 2.2W power dissipation from the comb decimator; the transistor count is 4525.