Abstract

In this paper new dynamic charge injection E/D logics are presented and compared with traditional dynamic ones such as TDFL (Two Phase Dynamic Fet Logic). The main drawbacks of TDFL will be analyzed together with the advantages offered with respect to the static DCFL based topologies; a tentative structure has been derived (MTDFL - Modified TDFL) to comply with the VLSI requirements; then the advantages of the charge injection principles applied to the design of new logic topologies are inspected and used in a pseudo complementary structure (PCDL - Pseudo Complementary Dynamic Logic). The results of the simulations for these structures are presented together with the design of a 4-bits pipelined adder simulated at 2 GHz with a power dissipation 20 times lower than a DCFL implementation.