1.5 Gb/s, 6.6 mW 8-bit multiplexer using two-phase dynamic FET logic

Lassen, Peter S. ; Long, Stephen I. (1994) 1.5 Gb/s, 6.6 mW 8-bit multiplexer using two-phase dynamic FET logic. In: Gallium Arsenide Applications Symposium. GAAS 1994, 28-30 April 1994, Turin, Italy.
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Abstract

GaAs Two-Phase Dynamic FET Logic (TDFL) gates are used in the design of a high-speed, low-power 8-bit multiplexer. Operation of the multiplexer is demonstrated at 1.5 Gb/s with an associated power dissipation of 6.6 mW. The operation of the multiplexer demonstrates the high equivalent gate count of TDFL gates, direct compatibility between TDFL and Direct-Coupled FET Logic (DCFL), and the advantages of shift register architectures when simple, low-power dynamic latches are available in GaAs circuits.

Abstract
Tipologia del documento
Documento relativo ad un convegno o altro evento (Atto)
Autori
AutoreAffiliazioneORCID
Lassen, Peter S.
Long, Stephen I.
Settori scientifico-disciplinari
DOI
Data di deposito
17 Feb 2006
Ultima modifica
17 Feb 2016 14:42
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