A low-power GaAs flip-flop

Kanan, R. ; Hochet, B. ; Kaess, F. ; Declercq, M. (1997) A low-power GaAs flip-flop. In: Gallium Arsenide Applications Symposium. GAAS 1997, 3-5 September 1997, Bologna, Italy.
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Abstract

This paper describes a low-power high speed flip-flop in Gallium Arsenide (GaAs) called PCLF for Pseudo-Complementary Logic Flip-Flop. The PCLF offers attractive power saving without performance degradation and is fully compatible with existing FET logic families. It can be efficiently used in the VLSI ICs, as well as in multigabit/second SSI or MSI ICs. As an example a D-flip-flop, T-flip-flop and a 1/8 divider have been designed and fabricated, verifying the expected low power dissipation.

Abstract
Tipologia del documento
Documento relativo ad un convegno o altro evento (Atto)
Autori
AutoreAffiliazioneORCID
Kanan, R.
Hochet, B.
Kaess, F.
Declercq, M.
Settori scientifico-disciplinari
DOI
Data di deposito
23 Nov 2005
Ultima modifica
17 Feb 2016 14:22
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