A monolithic GaAs clock and data recovery circuit for 2.5 Gb/s NRZ data stream

Pallotta, Andrea ; Centurelli, F. ; Trifiletti, Alessandro (1997) A monolithic GaAs clock and data recovery circuit for 2.5 Gb/s NRZ data stream. In: Gallium Arsenide Applications Symposium. GAAS 1997, 3-5 September 1997, Bologna, Italy.
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Abstract

A GaAs monolithic clock and data recovery circuit for 2.5 Gb/s NRZ data stream has been designed and fabricated by using 0.3 mm HEMT technology from IAF FhG foundry. The main functions carried out by the IC are: signal amplification (25 dB), clock recovery and decision. The design is intended to achieve a complete 2.5 Gb/s receiver by using the IC and a LN preamplifier (transimpedance stage and limiting amplifier stage) placed in a DIL package. The overall scheme comprises about 200 active devices, used both for analog and digital blocks, uses a single rail bias (-4.5 V) and standard ECL output levels. The fabricated chip has been tested and measured by using a ceramic package and a small PCB, showing an input sensitivity of 30 mVpp and rms output jitter below 10 psec under 215-1 PRBS.

Abstract
Tipologia del documento
Documento relativo ad un convegno o altro evento (Atto)
Autori
AutoreAffiliazioneORCID
Pallotta, Andrea
Centurelli, F.
Trifiletti, Alessandro
Settori scientifico-disciplinari
DOI
Data di deposito
23 Nov 2005
Ultima modifica
17 Feb 2016 14:22
URI

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