Low-power GaAs multiplexer and demultiplexer

Jakobsen, Jens (1994) Low-power GaAs multiplexer and demultiplexer. In: Gallium Arsenide Applications Symposium. GAAS 1994, 28-30 April 1994, Turin, Italy.
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Abstract

For the implementation of high-complexity circuits operating at high speed, low-power circuits are essential in order to meet chip level and systems level power dissipation requirements. This paper presents the designs of a multiplexer and a demultiplexer. The circuits are implemented by using two-phase dynamic FET logic (TDFL). Two chips were designed. Each chip comprises a small system integrating normal TDFL logic, pass gates and domino logic as well as clock drivers. Measurements show that the multiplexer operates at 300MHz and the demultiplexer operates at 550MHz

Abstract
Document type
Conference or Workshop Item (Paper)
Creators
CreatorsAffiliationORCID
Jakobsen, Jens
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Deposit date
17 Feb 2006
Last modified
17 Feb 2016 14:42
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