Abstract

This paper compares three compatible normally-off classes of digital logic, namely DCFL, SDCFL and SFFL, that have been found to be suitable for Gallium Arsenide VLSI implementation. A Merged Logic approach that exploits the advantages of each of the logic classes to provide superior circuit performance is demonstrated. A design methodology using Ring Notation for mapping of logic in a systematic way is also presented and the underlying principles highlighted using the design of a Polynomial Evaluator Processing Element.