Transistor specifications and substrate defect's in GaAs test circuits

Fillard, J.P. ; Castagné, M. ; Gall, P. ; Bonnafe, J. (1990) Transistor specifications and substrate defect's in GaAs test circuits. In: Gallium Arsenide Applications Symposium. GAAS 1990, 19-20 April 1990, Rome, Italy.
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Abstract

It has been known for years that defects in GaAs wafers induce large perturbations and scattering in the specifications of transistors. Japanese workers (Y Nanishi) have performed extended investigations on this correlation using bidimensional mapping techniques whereas other people have used the so called Dense Row Pattern or matrix FET areas method. In this communication we present new results related to the inspection of microprecipitates revealed by Laser Scanning Tomography (LST). This high sensitivity technique allows us to obtain images of micropecipitates in the bulk material with especially high resolution and narrow sectioning specifications. It has been extended to the region underlying the surface just beneath the transistor channel. A statistical evaluation of the threshold voltage and the side gating effect has been studied and correlated with the neighbouring microprecipicates.

Abstract
Document type
Conference or Workshop Item (Paper)
Creators
CreatorsAffiliationORCID
Fillard, J.P.
Castagné, M.
Gall, P.
Bonnafe, J.
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DOI
Deposit date
02 Feb 2006
Last modified
17 Feb 2016 14:49
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