Characterisation, Modelling and Design of Bond-Wire Interconnects for Chip-Package Co-Design Insertion Loss (dB)

Chandrasekhar, Arun ; Stoukatch, Serguei ; Brebels, S. ; Balachandran, Jayaprakash ; Beyne, Eric ; De Raedt, W. ; Nauwelaers, Bart ; Poddar, Anindya (2003) Characterisation, Modelling and Design of Bond-Wire Interconnects for Chip-Package Co-Design Insertion Loss (dB). In: Gallium Arsenide applications symposium. GAAS 2003, 6-10 October 2003, Munich.
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Abstract

This work is a comprehensive experimental investigation of chip to package wirebond interconnects for chip-package co-design. Wirebonds are interconnect bottlenecks in RF design, but are difficult to avoid due to their low cost and manufacturing ease. We have shown measurements on wirebonds in coplanar configuration with different return paths and also the cross coupling. We have also extracted lumped and distributed models and demonstrate the excellent agreement with measurements atleast upto 15GHz. We have proposed multi-wirebonds as a potential solution for better impedance matching. Different types of inductors with Q-factors of upto 100 have also been illustrated. We show influence of encapsulant on wirebonds and finally we also demonstrate a methodology to extract the time-domain response from S-parameters.

Abstract
Tipologia del documento
Documento relativo ad un convegno o altro evento (Atto)
Autori
AutoreAffiliazioneORCID
Chandrasekhar, Arun
Stoukatch, Serguei
Brebels, S.
Balachandran, Jayaprakash
Beyne, Eric
De Raedt, W.
Nauwelaers, Bart
Poddar, Anindya
Settori scientifico-disciplinari
DOI
Data di deposito
17 Giu 2004
Ultima modifica
17 Feb 2016 13:56
URI

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