Abstract

A model for simulating the DC characteristics of the gate junction in High Electron Mobility Transistors is presented. The equations for the gate current of FET's in the SPICE simulator are modified to account of the HEMT gate current in a wide range of bias conditions. It is proven that a four-diodes model yields to a satisfactory agreement with the experimental data. The presented model can be employed either by implementing the modified equations in the simulator code or by a device macro modeling.