Partially depleted CMOS SOI technology for low power RF applications

Tinella, C. ; Gianesello, F. ; Gloria, D. ; Raynaud, C. ; Delatte, P. ; Engelstein, A. ; Fournier, J.M. ; Benech, Ph. ; Jomaah, J. (2005) Partially depleted CMOS SOI technology for low power RF applications. In: Gallium Arsenide applications symposium. GAAS 2005, 3-7 ottobre 2005, Parigi.

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Abstract

The low resistivity substrate that is used in bulk silicon processes (CMOS and BiCMOS) limits the integration of high-quality passives components and gives rise to severe substrate coupling issues. This paper will show how to take advantage of HR SOI to improve RF circuit performances as well as the effectiveness of HR SOI to reduce substrate coupling. Potentiality of mm-wave passive integration is also shown.

Abstract

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