A new gate process for the realization of lattice - matched HEMT on InP for high yield MMICs

Hoel, V. ; Bollaert, S. ; Wallart, X. ; Grimbert, B. ; Lepilliet, S. ; Cappy, A. (1998) A new gate process for the realization of lattice - matched HEMT on InP for high yield MMICs. In: Gallium Arsenide Applications Symposium. GAAS 1998, 5-6 October 1998, Amsterdam, The Netherlands.

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Abstract

A new gate process for the realization of ultra short gate HEMT on InP is presented. In this technology, the top of the gate is deposited on a Si3N4 layer. This gate process leads to small footprints, mechanically strong devices and good yield. Using this gate technology, HEMT with high Ft were realized and characterized. The influence of the Si3N4 removing was also investigated.

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