Lopez, J.F. ; Sarmiento, R. ; Nunez, A. ; Eshraghian, K.
(1996)
A 2ns/660mW GaAs 5Kbit ROM using low leakage current FET circuit (L2FC).
In: Gallium Arsenide Applications Symposium. GAAS 1996, 5-6 June 1996, Paris, France.
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Abstract
In this paper, a 5Kb it ROM is presented using a primitive-cell architecture based on a compensation technique, named Low Leakage Current FET Circuit (L2FC), whose main advantage relies on the fact that it has an extremely low noise margin sensitivity with fan-in compared with Direct Coupled FET logic (DCFL). This characteristic is found to be the key factor when implementing GaAs ROMs because of its degradation as the number of word lines is increased. The performance obtained using this structure demonstrates the effectivenes of this technique and its significant improvement on noise margin increase.
Abstract