Abstract

In this paper, a 5Kb it ROM is presented us­ing a primitive-cell architecture based on a compensation technique, named Low Leakage Current FET Circuit (L2FC), whose main advantage relies on the fact that it has an ex­tremely low noise margin sensitivity with fan-in compared with Direct Coupled FET logic (DCFL). This characteristic is found to be the key factor when implementing GaAs ROMs because of its degradation as the number of word lines is increased. The performance obtained using this structure demonstrates the effectivenes of this technique and its significant improvement on noise margin increase.