Saglam, M. ; Leo, E. ; Bozzi, M. ; Perregrini, L. ; Rodriguez-Gironés, M. ; Hartnagel, H.L.
(2002)
Fabrication, Testing, and Lumped Element Modeling of Planar Heterostructure Barrier Varactors.
In: Gallium Arsenide applications symposium. GAAS 2002, 23-27 september 2002, Milano.
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Abstract
In this paper we present a novel lumped element model of planar InGaAs/InAlAs/AlAs Heterostructure Barrier Varactors (HBVs) on InP substrate. HBVs with 30 and 40 ¹m anode diameters were fabricated as coaxial-type con¯guration to check the wafer quality and extract the intrinsic parameters. Planar HBVs mounted on a coplanar waveguide were fabricated and measured in the 0.5{26.5 GHz frequency range, at di®erent bias points up to 10 V. The measured S-parameters were ¯tted to the proposed equivalent circuit to extract the values of both the parasitic and intrinsic elements. Finally, the extracted equivalent circuit was used to calculate the theoretical tripling e±ciency at 450 GHz attainable with the fabricated HBVs.
Abstract
In this paper we present a novel lumped element model of planar InGaAs/InAlAs/AlAs Heterostructure Barrier Varactors (HBVs) on InP substrate. HBVs with 30 and 40 ¹m anode diameters were fabricated as coaxial-type con¯guration to check the wafer quality and extract the intrinsic parameters. Planar HBVs mounted on a coplanar waveguide were fabricated and measured in the 0.5{26.5 GHz frequency range, at di®erent bias points up to 10 V. The measured S-parameters were ¯tted to the proposed equivalent circuit to extract the values of both the parasitic and intrinsic elements. Finally, the extracted equivalent circuit was used to calculate the theoretical tripling e±ciency at 450 GHz attainable with the fabricated HBVs.
Document type
Conference or Workshop Item
(Poster)
Creators
Subjects
DOI
Deposit date
17 Jun 2004
Last modified
17 Feb 2016 13:39
URI
Other metadata
Document type
Conference or Workshop Item
(Poster)
Creators
Subjects
DOI
Deposit date
17 Jun 2004
Last modified
17 Feb 2016 13:39
URI
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