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Ousset, M. ; Auvergne, D.
(1994)
Analytical delay model for Gallium Arsenide digital circuits.
In: Gallium Arsenide Applications Symposium. GAAS 1994, 28-30 April 1994, Turin, Italy.
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Abstract
We present in this paper an analytical method for the evaluation of the performances of the BFL (Buffered FET Logic configuration) GaAs structures. Based on a representation of the average imbalance current, it allows direct evaluation of delays, with clear indication of technological, structural and environmental parameters, allowing the definition of sizing and optimization criteria. This method is validated through SPICE simulations on different configurations.
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