Abstract

Emitter Coupled Logic (ECL) gate is a good candidate for gigabit logic when one uses GaAs/GaAlAs Heterojunction Bipolar Transistor (HBT). With the double mesa process, intercon­nections between the 5 transistors of the elemental gate have to climb the emitter and base mesas, leading to lack of density. A more compact design of the ECL gate has been achieved, in which the transistors are directly connected on the top of the base mesa. The DC characteristics of this gate are similar to these obtained with conventional gate design and the surface is reduced by a factor 1.6.