Mueller, J.-E. ; Gerlach, U. ; Madonna, G.L. ; Pfost, M. ; Schultheis, R. ; Zwicknagl, P.
(2000)
A 3V small chip size GSM HBT power MMIC with 56% PAE.
In: Gallium Arsenide applications symposium. GAAS 2000, 2-6 october 2000, Paris.
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Abstract
A three stage 56% power added efficiency (PAE) InGaP/GaAs HBT power MMIC for use in GSM applications (900MHz) is described. An output power of 2.7W is obtained at the connectors of the evaluation board with a single supply voltage of 3.2V. The large signal gain is in excess of 32dB and the dynamic range for power control exceeds 80 dB. The chip size of only 2mm² allows housing in a tiny plastic package (TSSOP10) which occupies less than one half of the board area compared to packaged GSM devices before. For circuit design an accurate electrothermal large-signal HBT model is used. For characterisation of large emitter area power transistors on-wafer large signal measurement techniques have been developed which assist model verification and provide new insights in the influence of harmonic load terminations. The design techniques employs two steps. In a first step on-wafer loadpull measurements provide reasonable conditions for output power, which are combined with appropriate small-signal simulations to fix th circuit topology in principal. In a second step refinements of the power performance are achieved by large-signal simulations.
Abstract
A three stage 56% power added efficiency (PAE) InGaP/GaAs HBT power MMIC for use in GSM applications (900MHz) is described. An output power of 2.7W is obtained at the connectors of the evaluation board with a single supply voltage of 3.2V. The large signal gain is in excess of 32dB and the dynamic range for power control exceeds 80 dB. The chip size of only 2mm² allows housing in a tiny plastic package (TSSOP10) which occupies less than one half of the board area compared to packaged GSM devices before. For circuit design an accurate electrothermal large-signal HBT model is used. For characterisation of large emitter area power transistors on-wafer large signal measurement techniques have been developed which assist model verification and provide new insights in the influence of harmonic load terminations. The design techniques employs two steps. In a first step on-wafer loadpull measurements provide reasonable conditions for output power, which are combined with appropriate small-signal simulations to fix th circuit topology in principal. In a second step refinements of the power performance are achieved by large-signal simulations.
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Settori scientifico-disciplinari
DOI
Data di deposito
17 Giu 2004
Ultima modifica
17 Feb 2016 13:40
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Tipologia del documento
Documento relativo ad un convegno o altro evento
(Atto)
Autori
Settori scientifico-disciplinari
DOI
Data di deposito
17 Giu 2004
Ultima modifica
17 Feb 2016 13:40
URI
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