Abstract

Two-dimensional transient simulation of GaAs FETs are performed in which substrate traps, surface states and impact ionization of carriers are considered. The mechanisms of lag phenomena and so-called power compression are discussed. It is shown that the drain-lag occurs mainly due to substrate traps, and the gate-lag mainly by surface states. Obtained quasi-pulsed I-V curves clearly indicate that the power compression can occur both due to substrate traps and due to surface states. Effects of the impact ionization on these phenomena are also discussed.